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4.3 Defining Interrupt Service Routines
For the native mode devices you may write special-purpose code to service hardware interrupts.  This
may be useful, for example, to add some interrupt-driven capability to your program that is not directly
supported by ZBasic.  The syntax for defining an interrupt service routine is similar to that for defining a
subroutine, illustrated here by example.  Note that the definition of an ISR does not allow parameters but
the parentheses are, nonetheless, required.
ISR Timer1_CompB()
  ' place the ISR code here
End ISR
The ISR name following the ISR keyword must be valid for the underlying processor, a list of which is
shown in the table below.  The ISR names are not case sensitive.  More specific details about each
interrupt may be found in the datasheet for the corresponding AVR processor.  The shaded entries in the
table below denote ISR names that may not be used because their functionality is essential to the
operation of the ZX infrastructure.  For other ISR names, you may define an ISR provided that it does not
conflict with an ISR that is needed for System Library routines that you use in the application.  For
example, you may provide an ISR for the Timer1 Input Capture interrupt as long as you do not use the
ZBasic System Library routine InputCapture() in your program.  In the table below, the superscript, if any,
indicates an ISR that may be automatically supplied by the compiler.  The notes below the table describe,
in general terms, when they might be automatically supplied. The descriptions of the System Library
routines describe with more specificity which ISRs they require, if any, and the conditions under which
they will be required.
Available ISR Names by CPU Type
mega644P 
mega1281
mega1280
ADC
ADC
ADC
ANALOG_COMP¹
ANALOG_COMP¹
ANALOG_COMP¹
EE_READY
EE_READY
EE_READY
INT0¹
INT0¹
INT0¹
INT1¹
INT1¹
INT1¹
INT2¹
INT2¹
INT2¹
INT3¹
INT3¹
INT4¹
INT4¹
INT5¹
INT5¹
INT6¹
INT6¹
INT7¹
INT7¹
PCINT0¹
PCINT0¹
PCINT0¹
PCINT1¹
PCINT1¹
PCINT1¹
PCINT2¹
PCINT2¹
PCINT2¹
PCINT3¹
SPI_STC
SPI_STC
SPI_STC
SPM_READY
SPM_READY
SPM_READY
TIMER0_COMPA²
TIMER0_COMPA³
TIMER0_COMPA³
TIMER0_COMPB
4
TIMER0_COMPB
TIMER0_COMPB
TIMER0_OVF
TIMER0_OVF
TIMER0_OVF
TIMER1_CAPT
5
TIMER1_CAPT
5
TIMER1_CAPT
5
TIMER1_COMPA
6
TIMER1_COMPA
TIMER1_COMPA
TIMER1_COMPB
7
TIMER1_COMPB
7
TIMER1_COMPB
7
TIMER1_COMPC
7
TIMER1_COMPC
7
TIMER1_OVF
5
TIMER1_OVF
5
TIMER1_OVF
5
TIMER2_COMPA³
TIMER2_COMPA²
TIMER2_COMPA²
TIMER2_COMPB
TIMER2_COMPB
4
TIMER2_COMPB
4
TIMER2_OVF
TIMER2_OVF
TIMER2_OVF
TIMER3_CAPT
5
TIMER3_CAPT
5
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